Labview Fpga 8 Bit Universal Shift Register

Practical Context: Here we had 8 inputs as a std_logic_vector that went from 7 down to 0 ( Wrote some verilog to send signals to DS/STCP/SHCP pins, to have the LEDs run.

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Here we had 8 inputs as a std_logic_vector that went from 7 down to 0 ( Wrote some verilog to send signals to DS/STCP/SHCP pins, to have the LEDs run.

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Here we had 8 inputs as a std_logic_vector that went from 7 down to 0 (
Wrote some verilog to send signals to DS/STCP/SHCP pins, to have the LEDs run.

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